1. Field of the Invention
This invention relates generally to a large scale integrated (LSI) circuit and, more particularly in directed to an LSI circuit for converting pulse code modulated (PCM) data to an analog signal.
2. Description of the Prior Art
When a digital audio signal recorded on a record medium, such as a compact disc or the like, is converted to an analog audio signal, a digital-to-analog converter (hereinafter, referred to as a D/A converter) is used therefor. In the conventional D/A. converter, a digital audio signal of a predetermined bit number is converted to a staircase signal by code-to-voltage converting means and the thus converted staircase signal is supplied to a low-pass filter so as to produce an analog audio signal.
In the staircase signal converted by the code-to-voltage converting means a noise or a glitch occurs as a perturbation in the pulse waveform having a relatively short duration between respective staircases. Further, noise occurs due to the conversion accuracy of the converting means, so that, the sound quality of the resultant converted analog audio signal is deteriorated.
More specifically, in a weighting circuit used in the D/A converter, the following problems arise:
(1) An output voltage is determined by either a voltage-dividing ratio of a resistance/capacitance of an addition of currents. Thus, a fluctuation of the ratio between the resistance and the capacitance leads directly to a fluctuation of the output voltage. Typically, the fluctuation of the ratio between the resistance and the capacitance in an LSI circuit, that is, due to the manufacturing process, is within a range of approximately 0.1 to 1.0% which results in a maximum accuracy of the D/A converter of 10 to 14 bits. As a result, a trimming process is generally performed on the elements However, in order to perform the D/A conversion with an accuracy of 16 bits, a highly accurate trimming technique is required which cannot be easily performed; and
(2) The glitch occurs due to the opening and closing timings of the latch circuits and the switching circuits being shifted, and is generally removed by a so-called deglitcher circuit. However, the tone quality is deteriorated by the switching noise of the deglitcher circuit or by a droop, a distortion, an overshoot and the like.
In an attempt to eliminate the defects encountered with the conventional D/A converter, numerous combined systems involving a noise shaping method and a one-bit D/A converting method have been recently developed.
Examples of the above-described combined systems include a .DELTA.-to-.SIGMA. converting system developed by the Philips Corp., and a multi-stage noise shaping (MASH) system developed by the Nippon Telegram and Telephone Corporation. An overall arrangement of such a combined system is illustrated in the block diagram of FIG. 1.
As shown in FIG. 1, a digital audio signal, for example, of 16 bits, having a sampling rate fs is applied through an input terminal 1 to a digital interpolation filter 2, in which the signal is converted to a noise-shaped digital signal having 1 to 4 bits and a sampling rate of 32 to 256 fs. The resultant digital signal is supplied to a D/A converter 3 in which an analog signal is produced and outputted having an accuracy of 1 to 4 bits. The outputted analog signal is further processed by an output buffer 4 and a low-pass filter 5; whereupon, an analog audio signal is delivered to an output terminal 6.
In the D/A conversion of the noise shaping system, a shaping operation is performed for distributing a noise component in the high frequency region so as to produce an analog output with an improved signal-to-noise (S/N) ratio. Further, the D/A conversion of one bit is performed without the aforementioned defects, that is, the occurrence of glitches and the deterioration of the accuracy.
Systems have been proposed for the digital-to-analog conversion of pulse width modulation (PWM) signals in which a binary digital signal having 1 to 4 bits is processed so as to obtain a multi-level analog signal.
An overall arrangement of the D/A conversion in the noise-shaping system will be explained with reference to FIGS. 2 and 3A-3D.
As shown in FIG. 2, a noise-shaped digital signal, for example, of 3 bits, is supplied through an input terminal 7 to a read-only memory (ROM) 8 which outputs a pulse b which is pulse-width-modulated in the time direction. The waveform of the pulse b is represented in FIG. 3B. The output pulse b from ROM 8 is supplied to a D-type flip-flop circuit 9, in which the pulse is sampled by a clock signal, which is applied to an input terminal 10 from a crystal oscillation clock (not shown), so as to absorb jitter components.
The output signal from D-type flip-flop 9 is supplied through a complementary metal oxide semiconductor (CMOS) converter 11 to a low-pass filter 12 from which an analog output signal is coupled to an output terminal 13.
An operation of the circuit arrangement of FIG. 2 will now be described for the case in which the digital signal applied to the input terminal 7 changes levels as at "1", "2", "3" in FIG. 3A.
The noise-shaped digital signal supplied through input terminal 7 to the ROM 8 causes the latter to output the pulse signal b having a pulse width proportional to the digital values as shown in FIG. 3B. The pulse b is sampled by the D-type flip-flop 9 and the output sampled signal is supplied to CMOS inverter 11 which derives a pulse c having a predetermined phase relative to the pulse b, as represented in FIG. 3C. The pulse c is smoothed by the low-pass filter 12, and is supplied to output terminal 13 as an output signal d have a gradually increasing voltage level as shown by the waveform diagram of FIG. 3D.
The output c, from CMOS inverter 11, is a voltage signal in binary form which represents the GND and +V.sub.DD value, so that, although the aforementioned D/A converter produces a multi-value analog output, this D/A converter is generally regarded as a one-bit D/A converter. Accordingly, the prior-art weighting circuit, as previously described, is not required, so that, D/A conversion can be performed which is free from the problems of accuracy deterioration and the occurrence of glitches.
In the D/A converter of the pulse width modulation system for generating the PWM wave, an output buffer circuit must be provided as the final stage circuit which is, for example, composed of two field effect transistors (FETs) 21 and 22 as shown in FIG. 4. The PWM wave, from the converting circuit, is supplied to a terminal 23 which is connected to the gate electrodes of the two field effect transistors 21 and 22. The source electrode of the P-channel field effect transistor 21 is connected to a voltage source terminal V.sub.DD, whereas the source electrode of the other or N-channel field effect transistor 22 is connected to a voltage source terminal V.sub.SS. The drain electrodes of the two field effect transistors 21 and 22 are connected together and coupled to a common output terminal 24. Thus, the PWM wave is supplied through the output buffer circuit to output terminal 24.
In the previously described output buffer circuit, the ON resistance values of P-channel and N-channel transistors 21 and 22, respectively, must be made equal to each other, so as not to deteriorate the signal-to-noise (S/N) ratio of the output signal. For example, when the ON resistance values of the P-channel and N-channel transistors 21 and 22, respectively, are equal to each other, the S/N ratio of the audio signal delivered from the D/A converter is higher than 120 dB, which results in a high quality audio signal. On the other hand, if the ON resistance values of the P-channel and N-channel transistors 21 and 22, respectively, are not equal to each other, the S/N ratio of the audio signal is only approximately 80-100 dB. In an attempt to avoid this defect, it has been proposed to insert a resistor between the source electrode, for example, between the P-channel transistor 21 and the voltage source terminal V.sub.DD, for adjusting the ON resistance values. However, the ON resistance values fluctuate due to changes in ambient temperature. For example, as shown in FIG. 5, if the ambient temperature is changed by 50.degree. C., this is, from 25.degree. C. to 75.degree. C., the ON resistance value is changed from 10.OMEGA. to 11.OMEGA., that is, by about 10%. Thus, since the ON resistance values fluctuate due to temperature change adjusting the ON resistance values at a particular ambient temperature by the means of resistor. Does not insure that the ON resistance values will remain equal at other ambient temperatures.
In the circuit arrangement shown in FIG. 2, the output PWM pulse from ROM 8 can be regarded as an analog-converted signal. Thus, the D-type flip-flop 9, the inverter 11 and the circuits succeeding the output of the ROM 8, can be regarded as an analog signal processing portion. On the other hand, the ROM 8 and the digital interpolation filter 2 (FIG. 1) constitute a digital signal processing portion and these digital elements can be readily formed on a single LSI chip.
When a plurality of signal processing portions are formed on the same chip, it is frequently observed that one signal processing portion exerts a negative influence on the other signal processing portion. More specifically, when, for example, the digital signal processing portion and the analog signal processing portion are formed on the same chip, a signal in the form of a pulse wave, which is processed by the digital signal processing portion, exerts a negative influence upon a signal within the analog signal processing portion, so as to superimpose a noise component upon an output signal of the analog signal processing portion.